The present invention relates generally to a motherboard adopting Peripheral Component Interconnect (PCI) Express bus, and more particularly to an apparatus and method for testing the physical link paths of the same.
There has been a need of a higher-bandwidth, faster-speed interconnect technology for Personal Computer (PC) systems and peripherals. The low data transfer rate of the conventional PCI bus has become a bottleneck for developing faster computer systems. A standard 64-bit PCI running at 66 MHz of clock frequency has a data transfer rate of 533 MB/s. This imposes a limit on the development of software and peripherals.
PCI Express, formally known as the third generation I/O, has been introduced recently. A PCI Express link consists of multiple, point-to-point serial connections called lanes. Multiple lanes can be used to create an I/O interconnect whose bandwidth is linearly scalable. The first generation of PCI Express technology provides an effective 2.5 GB per second per lane per direction of raw bandwidth. This will greatly improve the performance of the computer systems, particularly in graphic processing.
Given that the PCI devices still dominate the current market, more PCI Express compatible devices need to be brought to the market. Thus, there is a need for proper methods and tools for testing the newly developed PCI Express devices.
As such, what is needed is a cost-efficient apparatus and method for testing the physical PCI Express link paths on a motherboard using PCI Express devices.